1. Field of the Invention
The present invention relates to a non-volatile memory, and particularly to a memory cell structure of a ferroelectric memory using a ferroelectric thin film.
2. Description of the Related Art
There has recently been much growing interest in a memory using a ferroelectric substance. A ferroelectric memory stores therein information through the use of spontaneous polarization of the ferroelectric substance. Therefore, if a voltage is applied to the ferroelectric substance to align polarization in the same direction, then the polarization remains (this is called xe2x80x9cremnant polarizationxe2x80x9d) even after the power is turned off. Thus, the ferroelectric memory can be utilized as a nonvolatile memory. The conventional non-volatile memory needs a high voltage of 10 V or higher upon writing of data therein, and a write speed thereof comes into the world of microseconds (msec). On the other hand, the ferroelectric memory is capable of polarization reversal at a few V, and a reversal speed thereof comes into the world of nanoseconds (nsec). The ferroelectric memory has been expected as a non-volatile memory capable of performing a low-voltage operation and a high-speed operation from such a background. A currently developed/proposed ferroelectric memory comprises a memory cell comprised of a MOS transistor and a ferroelectric capacitor.
However, the conventional ferroelectric memory has the possibility that when the state of polarization of the ferroelectric capacitor lies in a direction indicated by an arrow ↓, the application of a voltage lying in the same direction as the polarization to the ferroelectric capacitor will be maintained. At this time, so-called in-print deterioration is developed and interferes with a reverse operation of the polarization of the ferroelectric capacitor from the direction indicated by an arrow ↓ to that indicated by an arrow ↑, thus causing a possibility that misreading will be brought about. Incidentally, the in-print deterioration means a shift or displacement of a hysteresis loop, which is developed due to the temperature, pressure, mechanical stress, etc. in the manufacturing process.
It is known that while the writing of data into a memory cell is carried out by application of a voltage having an H level to a data line, the polarization of the ferroelectric capacitor is slightly reduced. This is called xe2x80x9cdepolarizationxe2x80x9d. The time constant of the depolarization is 1 msec or more, and the depolarization is normally unsaturated even after a word line is brought to an L level. In other words, this means that the polarization continues to decrease even after the ferroelectric capacitor is brought to a floating state.
Since an electrical charge produced in an electrode does not change even if the ferroelectric memory is reduced in polarization, a potential is developed across the ferroelectric capacitor. The direction of an electric field thereof is the same as the direction of polarization. Since the memory cell is polarized in a direction indicated by an arrow ↑, a potential having an H level is developed at a node on the select transistor side of the ferroelectric capacitor. Since, however, the select transistor is normally an N channel MOS transistor, a positive potential applied to the node on the select transistor side of the capacitor is hard to be discharged. Thus, the voltage lying in the same direction as the polarization continues to be applied to the ferroelectric capacitor for a while.
With the foregoing in view, it is therefore an object of the present invention to provide a ferroelectric memory capable of, when the state of polarization of a ferroelectric capacitor is in a direction indicated by an arrow ↓, restraining in-print deterioration, and smoothly performing a reverse operation of the polarization of the ferroelectric capacitor from the direction indicated by an arrow ↓ to that indicated by an arrow ↑, and carrying out a normal read operation.
According to one aspect of the present invention, for achieving the above object, there is provided a ferroelectric memory comprising a memory cell including a select transistor whose control electrode, first electrode and second electrode are respectively connected to a word line, a bit line and a first node, a ferroelectric capacitor whose first electrode and second electrode are respectively connected to the first node and connected to a plate line through a second node, and a resistor connected between the first node and the second node.